In this course, we will cover how modern processors are designed to achieve high performance under which restrictions. We will cover the topics related to: instruction set design; processor micro-architecture and pipelining; cache and virtual memory organizations; protection and sharing; I/O and interrupts; in-order and out-of-order superscalar architectures; memory models and synchronization; embedded systems; and parallel computers.
Since this course is a professional masters course, we will focus a bit more on pragmatic topics including architectural knowledge for performance engineering, and industry trends and outlook.
Lecturer: Sang-Woo JunDate | Title |
2023-10-02 | Lecture 1: Introduction, Moore's Law |
2023-10-04 | Lecture 2: Hardware-Software Interface
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2023-10-09 | Lecture 3: ISA Encoding and Complexity
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2023-10-11 | Lecture 4: Digital Circuits Why and How
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2023-10-16 | Lecture 4: Processor Design Constraints |
2023-10-18 | Lecture 5: Pipelining |
2023-10-23 | Lecture 5.5: Fast and Correct Pipelining |
2022-10-25 | Lecture 6: Explicit Parallelism
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2023-11-01 | Lecture 7: Caches and the memory system
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2023-11-13 | Lecture 8: Architectural support for the Operating System
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2023-11-20 | Lecture 9: Virtual Memory |
2023-11-27 | Lecture 10: Multiprocessing |
2023-12-01 | Lecture 13: Datacenter architecture |
2023-12-03 | Lecture 11: GPU Introduction |